There are basically two conventional methods for providing electrical isolation between integrated components on a silicon chip, namely, junction isolation and "isoplanar" oxide isolation, the latter being disclosed in U.S. Pat. No. 3,648,125. However, isoplanar oxide isolation suffers from the fact that the minimum width of the isolation regions is limited to the minimum resolvable line width of the photolithography used to fabricate the isoplanar devices. Also, as recited in co-pending application Ser. No. 170,907 filed on July 21, 1980, when the isolation groove is too large, it is difficult to fill this region by oxidizing said groove for temperatures would be required which result in serious damage to the isoplanar components unless the semiconductor structure was modified to reduce the high temperature effects.
In applicant's co-pending application Ser. No. 170,907, the difficulty in filling the isolation moat, which is desirable in applying electrical interconnects to the integrated circuit, was overcome by employing an electrically insulative resin which could be applied to the silicon body at a substantially lower temperature than that required for the formation of silicon oxide. A preferred resin was thought to be a polyimide. However, it was recognized in the present invention that the isolation problem could be solved alternatively by etching grooves in the semiconductor body which are so narrow in width that the growth of oxide on the groove walls would not require subjecting the integrated circuit to high temperatures for long periods of time. Before the present invention, however, it was impossible to fabricate such narrow grooves due to the limitations in photolithography.
Photolithography has also been used in constructing electrical devices of fairly narrow widths. Examples of such devices are resistors, diodes, and gate elements for silicon gate MOSFET transistors used in integrated circuits. It was recognized that if the gate elements could be reduced in size, more active elements could be placed upon a single silicon chip, thereby reducing overall cost of the integrated circuit. The reduction in area also produces a reduction of parasitic capacitance thereby reducing minimum response times of the integrated circuit elements. Furthermore, if one were able to fabricate gate elements for silicon gate transistors having shorter channels, the MOS transistors would possess exceptional speed with lower threshold voltages.
As stated previously, the desired results, as outlined above, are not achievable when relying on conventional photolithography. Under optimum conditions using ultra-violet light and negative photoresists, the minimum resolvable line width in conventional photolithography is approximately four microns (40,000 A). By using a positive photoresist, this minimum can be reduced to the range of two to three microns. Recently, electron beam photolithography has produced minimum line widths of one micron. Also, as recognized in U.S. Pat. No. 3,648,125, the use of photoresist masking has the further disadvantage of presenting pin hole imperfections to the photo-sensitive material which can produce a number of unacceptable results, the nature of which depend upon where the pin hole defects appear on the integrated circuit.
It is an object of the present invention to provide a means for electrically isolating active components on an integrated circuit without the disadvantages as outlined above.
It is a further object of the present invention to provide a method for constructing electrical devices of narrow widths.
It is yet another object of the present invention to provide isolation regions which are narrower than those achievable through the use of conventional photolithography.
It is still another object of the present invention to provide a means for fabricating isolation widths of approximately 1,000-20,000 A.
It is yet a further object of the present invention to produce gate elements for silicon gate transistors having exceptional speed due to short channels and low capacitance.